!pr0
!lm12
!rm75
New Enhanced 6502 Nearly Here!.............Bob Sander-Cederlof

Nigel Nathan from Micro-Mixedware in Stow, MA, sent me some copies of reference material for the new 65C02 chip.  This is the enhanced CMOS version, soon to be available from GTE and Rockwell.

Nigel's interest was that I might produced an enhanced S-C Macro Assembler to accommodate the new opcodes and addressing modes.  I not only might...I did it right away!  It is ready now, although you may have some difficulty getting the chips for a few more months.

Rockwell is sampling the 65C02 now, and scheduled for production in February.  Rockwell is also readying an entire family of CMOS products to go with the 65C02, including 2Kx8 CMOS static RAM and multi-byte parallel interfaces.

The 65C02 is expected to be plug-compatible with the 6502 in your Apple II.  In fact, Cliff Whitaker of Rockwell told me that the first chips they made were tested by plugging them into Apples.  Hopefully you will be able to simply plug them in and start using the new opcodes.  If true, then I will probably become a source for these chips.

What enhancements did they make?  According to the GTE document, some "bugs" in the 6502 design were corrected:

!lm+8
!pp-3
*  Indexed addressing across a page boundary no longer causes a false read at an invalid address.

*  Invalid opcodes are now all NOPs, rather than doing exotic things such as I described in the March 1981 AAL.

*  JMP indirect at a page boundary now operates correctly, at a cost of one additional cycle.

*  Read/modify/write opcodes (like INC, DEC, and the shifts) now perform two reads and one write cycle rather than one read and two writes.

*  The D-status bit is now set to binary mode (D=0) by reset; it used to be indeterminate.

*  The N-, V-, and Z-status bits are now valid after ADC or SBC in decimal mode (D=1); they used to be invalid, requiring special tests.  The cost is one additional cycle for all ADCs and SBCs in decimal mode.

*  An interrupt after fetch of a BRK opcode defers to the BRK.  It used to cause the BRK to be ignored.
!pp0
!lm-8
!np
The Rockwell literature makes reference to the following new opcodes, or new addressing modes for old opcodes:

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80   BRA rel    Branch Always

12   ORA (zp)   )
32   AND (zp)   )
52   EOR (zp)   )  new addressing mode:
72   ADC (zp)   )
92   STA (zp)   )  zero-page indirect
B2   LDA (zp)   )
D2   CMP (zp)   )  without indexing
F2   SBC (zp)   )

04   TSB zp     Test and set bits
14   TRB zp     Test and reset bits
34   BIT zp,X   new addressing mode for BIT
64   STZ zp     Store Zero
74   STZ zp,X     "    "

07-77   RMB b,zp   Reset bit b in zp
87-F7   SMB b,zp   Set bit b in zp

89   BIT imm    new addressing mode for BIT

1A   INC        Increment A-register
3A   DEC        Decrement A-register
5A   PHY        Push Y
7A   PLY        Pull Y
DA   PHX        Push X
FA   PLX        Pull X

0C   TSB abs    Test and set bits
1C   TRB abs    Test and reset bits
3C   BIT abs,X  new addressing mode for BIT
7C   JMP (abs),X   new addressing mode for JMP
9C   STZ abs    Store zero

9E   STZ abs,X  Store zero

0F-7F   BBR b,zp,rel   Branch if bit b in zp is zero
8F-FF   BBS b,zp,rel   Branch if bit b in zp is one
!lm-5

Let your imagination run wild with all the great ways to use these new opcodes!  If you feel the need for the ability to assemble them now, the Cross Assembler upgrade for the 65C02 is available for $20 to subscribers of the Apple Assembly Line who already own the S-C Macro Assembler.
